Responsibilities
- Develop our Electrical Analysis methodology and infrastructure to enable the verification flow of large HPC SoCs
- Perform full chip analysis debug and closure of all EA flows, including IR, IVD, EM for signal and power
- Provide input to full chip floorplan and guidance to the implementation teams throughout the project to enable early convergence and final closure
- Collaborate with Technology team and CAD partners to drive closure targets and signoff criteria
- Design and validate Power Distribution Networks optimized for best PPA in specific IPs
Requirements
- Experience with industry standard EA tools (Apache Redhawk, Cadence Voltus)
- Understanding of package modeling techniques for full level power analysis
- Expertise in EA convergence issues associated with high performance designs in advanced process nodes (static and dynamic IR driven timing closure)
- Strong scripting skills in tcl and python
- Ability and taste for solving complex problems, efficient written and verbal communication, excellent organization skills
- Self starter and highly motivated
- Ability to work cross-functionally
Salary
Competitive
Monthly based
Location
Bengaluru, Karnataka, India
Job Overview
Location
Bengaluru, Karnataka, India