Responsibilities
- As a lead, you will lead an engineering team responsible for designing, implementing and executing a subsystem silicon bringup plans, including functional and performance tests, to validate the subsystem for the silicon product to meet the product requirements.
- Collaborate with cross-functional teams including design, architecture, firmware, and software to ensure successful subsystem integration and validation.
- Work with vendors and partners to ensure successful subsystem bringup and validation, including reviewing and providing feedback on vendor documentation, and coordinating with vendor support teams.
- Debug and root-cause issues found during subsystem bringup and validation, and work with cross-functional teams to implement corrective actions.
- Drive continuous improvement of subsystem bringup and validation processes and methodologies, including automation, tool development, and documentation.
- Maintain up-to-date knowledge of the subsystem technology and industry trends.
Requirements
- In-depth knowledge of architecture, microarchitecture, and software interface of the subsystem.
- Experienced level knowledge C/C++ and Python.
- Relevant knowledge of verification methodologies, Verilog simulation, waveform viewers, and emulation.
- Experience in silicon debug for logic, software, and physical issues
- Strong ability to triage issues and develop environment and tools.
- Excellent skills in problem solving, written and verbal communication, excellent organization skills, and highly self-motivated.
- Ability to work well in a team and be productive under aggressive schedules.
Education & Experience
- PhD, Master’s Degree or Bachelor’s Degree with more than 5 years of experience in technical subject area.
Salary
Competitive
Monthly based
Location
Puli Township, Taiwan, Taiwan
Job Overview
Location
Puli Township, Taiwan, Taiwan