Responsibilities
- In-charge of engineering sample planning and delivery during NPI phase.
- Create test plans for SoC characterization across PVT corners, collect and analyze data, and implement voltage guard-bands for DVFS.
- Conduct spice to silicon correlation analysis and provide feedback to improve design to ensure silicon meets sign-off specifications.
- Incorporate product binning requirements into ATE HVM test programs.
- Analyze test data to identify trends, improve test coverage, and optimize test times.
Requirements
- Hands-on product engineering experience in complex SoC systems on advanced technology nodes (sub 5nm)
- Proven expertise Python (or other scripting languages), JMP, YMS software (e.g. Optimal+, DataConductor, etc.)
- Strong understanding of semiconductor device physics, testing methodologies, and statistical analysis
- Knowledge of FA techniques (like laser stimulation, LVx) for conducting fault isolation on complex designs.
- Experience with high-speed digital and mixed-signal testing.
- Strong communication and interpersonal skills, with the ability to effectively collaborate with cross-functional teams
Education and Experience
- Bachelor’s or Master’s Degree in technical subject area with 10+ years relevant work experience
Salary
Competitive
Monthly based
Location
Puli Township, Taiwan, Taiwan
Job Overview
Location
Puli Township, Taiwan, Taiwan