Responsibilities
- Own block level design from RTL-to-GDSII and drive synthesis, floor-planning, place & route, timing closure, and signoff.
- Work extensively with Micro-architects to perform feasibility studies and explore performance, power & area (PPA) tradeoffs for design closure.
- Develop physical design methodologies and customize recipes across various implementation steps to optimize PPA.
- Work with a multi-functional engineering team to implement and validate physical design by running all signoff flows such as Timing, Power, EM/IR, PDV.
Requirements
- Knowledge using synthesis, place & route, analysis and verification CAD tools.
- Familiarity with logic & physical design principles to drive low-power & higher-performance designs.
- Knowledge of scripting in some of these languages: Unix, Perl, Python, and TCL.
- Good understanding of device physics and experience in deep sub-micron technologiesKnowledge of Verilog and SystemVerilog.
- Excellent skills in problem solving, written and verbal communication, excellent organization skills, and highly self-motivated.
- Ability to work well in a team and be productive under aggressive schedules.
- PhD, Master’s Degree or Bachelor’s Degree in technical subject area
Salary
Competitive
Monthly based
Location
Santa Clara, California, United States
Job Overview
Location
Santa Clara, California, United States