Responsibilities
- Work closely with architect and design team to verify the feature sets of the DDR and HBM memory subsystem design
- Work closely with 3rd party IP vendors to validate the correctness of integration and custom features.
- Develop testplan and testbench
- Integrate and bring up VIPs such as DDR_PHY, DDR_Model as part of testbench
- Develop test stimulus, checkers and scoreboard in SystemVerilog/UVM
- Debug, regression and coverage closure
- Provide debug support to emulation and silicon-bring up teams.
- Able to work with teams across the continents
Key Qualifications
- Hands-on experience of verifying digital logic portion of DDR/HBM memory subsystem design
- Knowledge in JEDEC specification of LPDDRx/DDRx/HBMx
- Knowledge in the DDR DFI specification and protocol
- Knowledge in Reliability, availability and serviceability (RAS) features in the context of memory subsystem such as Error detection/correction and Encryption
- Master’s Degree or Bachelor’s Degree with 3-5 years of experience
Salary
Competitive
Monthly based
Location
Santa Clara, California, United States
Job Overview
Location
Santa Clara, California, United States
